Rakesh Kumar Singh1*, Prerona Sanyal2, Aloke Saha3
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This paper explores design idea for STI (Standard Ternary Inverter), NTI (Negative Ternary
Inverter) and PTI (Positive Ternary Inverter) using Normal Process Enhancement-type MOS devices without
threshold modifications. The working principle for aforesaid TI (Ternary Inverter) circuits is presented first. All
the TI circuits are designed and optimized next on TSMC 65nm CMOS technology applying BSIM4 device
parameter with 1.0V supply rail at 27°C temperature using S-Edit of Tanner EDA V.16. The physical design has
been performed using Microwind3.1. The trit value “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V
respectively. Designed circuits are validated by applying all possible test pattern dynamically and the transient
response through T-Spice simulation using W-Edit is presented. The PWL (Piece Wise Linear) input source has
been used to generate custom ternary input for transient simulation. The circuit performance parameters in terms
of device-count, area, propagation-delay, average-power and Power-Delay-Product (PDP) are evaluated and
recorded.